`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/16 09:24:34
// Design Name: 
// Module Name: hexseg8_sim
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module hexseg8_sim();
    reg clk_i = 1'b0;
    reg timer_rst_i = 1'b0;
    reg [7:0] d_i = 8'hab;
    reg [7:0] cnt;

    wire [7:0] bus_num1_o;
    wire [7:0] bus_num0_o;
    wire [7:0] digit_en_o;
    
    hexseg8 UUT(.clk_i(clk_i), .timer_rst_i(timer_rst_i), .d_i(d_i), .bus_num1_o(bus_num1_o), .bus_num0_o(bus_num0_o), .digit_en_o(digit_en_o));
    
    always #1 begin clk_i = ~clk_i; end
    initial begin
        #2
//        for (cnt=0 ; cnt<16 ; cnt=cnt+1) begin  // single digit from 0 to f
//            d_i[7:4] = cnt;
//            #100 begin end
//        end
        #1000 $stop;
    end
endmodule
